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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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7–32  
Chapter 7: User Flash Memory in MAX V Devices  
Software Support for UFM Block  
WRDI (Write Disable)  
After the UFM is programmed, WRDIcan be issued to set WENback to  
0, disabling WRITE  
and preventing inadvertent writing to the UFM. WRDIis issued through the following  
sequence, as shown in Figure 7–29:  
1. nCSis pulled low.  
2. Opcode 00000100is transmitted to set WENto  
0in the status register.  
3. After the transmission of the eighth bit of WRDI, the interface is in wait state  
(waiting for nCSto be pulled back to high). Any transmission after this is ignored.  
4. nCSis pulled back to high.  
Figure 7–29. WRDI Operation Sequence  
nCS  
0
1
2
3
4
5 6 7  
SCK  
SI  
8-bit  
Instruction  
04H  
MSB  
High Impedance  
SO  
MAX V Device Handbook  
January 2011 Altera Corporation  
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