7–34
Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
WRSR (Write Status Register)
The block protection bits(BP1and BP0) are the status bits used to protect certain
sections of the UFM from inadvertent write. The BP1and BP0status are updated by
WRSR. During WRSR, only BP1and BP0in the status register can be written with valid
information. The rest of the bits in the status register are ignored and not updated.
When both BP1and BP0are
0, there is no protection for the UFM. When both BP1and
BP0are , there is full protection for the UFM. BP0and BP1are set to 0 upon power-up.
1
Table 7–12 lists the Block Write Protect Bits for Extended mode, while Table 7–13 lists
the Block Write Protect Bits for Base mode. WRSRis issued through the following
sequence, as shown in Figure 7–31:
1. nCSis pulled low.
2. Opcode 00000001is transmitted into the interface.
3. An 8-bit status is transmitted into the interface to update BP1and BP0of the status
register.
4. If nCSis pulled high too early (before all the eight bits in Step 2 or Step 3 are
transmitted) or too late (the ninth bit or more is transmitted), WRSRis not executed.
5. nCSis pulled back to high to terminate the transmission.
Figure 7–31. WRSR Operation Sequence
nCS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
SI
8-bit
Instruction
01H
Status Register In
MSB
MSB
High Impedance
SO
Table 7–12. Block Write Protect Bits for Extended Mode
Status Register Bits
Level
UFM Array Address
Protected
BP1
BP0
0 (No protection)
3 (Full protection)
0
0
None
1
1
000 to 1FF
Table 7–13. Block Write Protect Bits for Base Mode
Status Register Bits
Level
UFM Array Address
Protected
BP1
BP0
0 (No protection)
3 (Full protection)
0
0
None
1
1
000 to 0FF
MAX V Device Handbook
January 2011 Altera Corporation
INTEL [ INTEL ]
