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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–29  
Software Support for UFM Block  
4. nCSis pulled back to high.  
For SPI Base mode, the SE instruction erases UFM sector 0. Because there are no  
choices of UFM sectors to be erased, there is no address component to this instruction.  
The SEoperation is always done through the following sequence in SPI Base mode:  
1. nCSis pulled low.  
2. Opcode 00100000is transmitted into the interface.  
3. nCSis pulled back to high.  
Figure 7–25. SECTOR-ERASE Operation Sequence for Extended Mode  
nCS  
0
1
2
3
4
5
6
7
8
9
10 11  
20 21 22 23  
SCK  
SI  
8-bit  
Instruction  
16-bit  
Address  
20H  
MSB  
MSB  
High Impedance  
SO  
Figure 7–26 shows the SECTOR-ERASEoperation sequence for Base mode.  
Figure 7–26. SECTOR_ERASE Operation Sequence for Base Mode  
nCS  
0
1
2
3
4
5 6 7  
SCK  
SI  
8-bit  
Instruction  
20H  
MSB  
High Impedance  
SO  
January 2011 Altera Corporation  
MAX V Device Handbook  
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