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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–33  
Software Support for UFM Block  
RDSR (Read Status Register)  
The content of the status register can be read by issuing RDSR. After RDSRis received,  
the interface outputs the content of the status register through the SOport. Although  
the four most significant bits (Bit 7 to Bit 4) do not hold valuable information, all eight  
bits in the status register will output through the SOport. This allows future  
compatibility when Bit 7 to Bit 4 have new meaning in the status register. During the  
internal program cycle in the UFM, RDSRis the only valid opcode recognized by the  
interface (therefore, the status register can be read at any time), and nRDYis the only  
valid status bit. Other status bits are frozen and remain unchanged until the internal  
program cycle is ended. RDSRis issued through the following sequence, as shown in  
Figure 7–30:  
1. nCSis pulled low.  
2. Opcode 00000101is transmitted into the interface.  
3. SIignores incoming signals; SOoutputs the content of the status register, Bit7first  
and Bit0last.  
4. If nCSis kept low, repeat step 3.  
5. nCSis pulled back to high to terminate the transmission.  
Figure 7–30. RDSR Operation Sequence  
nCS  
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23  
SCK  
SI  
8-bit  
Instruction  
05H  
MSB  
MSB  
High Impedance  
SO  
Status Register Out  
MSB  
MSB  
January 2011 Altera Corporation  
MAX V Device Handbook  
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