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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–27  
Software Support for UFM Block  
Figure 7–22 shows the READoperation sequence for Base mode.  
Figure 7–22. READ Operation for Base Mode  
nCS  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 23  
SCK  
SI  
8-bit  
Instruction  
8-bit  
Address  
03H  
MSB  
MSB  
High Impedance  
SO  
8-bit Data Out 1  
MSB  
8-bit Data Out 2  
MSB  
WRITE  
WRITEis the instruction for data transmission, where the data is written to the UFM  
block. The targeted location in the UFM block that will be written must be in the  
erased state (FFFFH) before initiating a WRITEoperation. When data transfer is taking  
place, the MSB is always the first bit to be transmitted or received. nCSmust be driven  
high before the instruction is executed internally. You may poll the nRDYbit in the  
software status register for the completion of the internal self-timed WRITEcycle. For  
SPI Extended mode, the WRITEoperation is always done through the following  
sequence, as shown in Figure 7–23:  
1. nCSis pulled low to indicate the start of transmission.  
2. An 8-bit WRITEopcode (00000010) is received from the master device. If internal  
programming is in progress, the WRITEoperation is ignored and not accepted.  
3. A 16-bit address is received from the master device. The LSB of the address will be  
received last. Because the UFM block can take only nine bits of address maximum,  
the first seven address bits received are discarded.  
4. A check is carried out on the status register (see Table 7–11) to determine if the  
WRITEoperation has been enabled, and the address is outside of the protected  
region; otherwise, Step 5 is bypassed.  
5. One word (16 bits) of data is transmitted to the slave device through SI  
.
6. nCSis pulled back to high to indicate the end of transmission.  
For SPI Base mode, the WRITEoperation is always performed through the following  
sequence in SPI:  
1. nCSis pulled low to indicate the start of transmission.  
2. An 8-bit WRITEopcode (00000010) is received. If the internal programming is in  
progress, the WRITEoperation is ignored and not accepted.  
3. An 8-bit address is received. A check is carried out on the status register (see  
Table 7–11) to determine if the WRITEoperation has been enabled, and the address  
is outside of the protected region; otherwise, Step 4 is skipped.  
January 2011 Altera Corporation  
MAX V Device Handbook  
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