欢迎访问ic37.com |
会员登录 免费注册
发布采购

5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
 浏览型号5M80ZE64I5N的Datasheet PDF文件第125页浏览型号5M80ZE64I5N的Datasheet PDF文件第126页浏览型号5M80ZE64I5N的Datasheet PDF文件第127页浏览型号5M80ZE64I5N的Datasheet PDF文件第128页浏览型号5M80ZE64I5N的Datasheet PDF文件第130页浏览型号5M80ZE64I5N的Datasheet PDF文件第131页浏览型号5M80ZE64I5N的Datasheet PDF文件第132页浏览型号5M80ZE64I5N的Datasheet PDF文件第133页  
Chapter 7: User Flash Memory in MAX V Devices  
7–25  
Software Support for UFM Block  
Opcodes  
Table 7–10 lists the 8-bit instruction opcodes. After nCSis pulled low, the indicated  
opcode must be provided. Otherwise, the interface assumes that the master device  
has internal logic errors and ignores the rest of the incoming signals. When nCSis  
pulled back to high, the interface is back to normal. nCSshould be pulled low again  
for a new service request.  
Table 7–10. Instruction Set for SPI  
Name  
Opcode  
Operation  
WREN  
WRDI  
RDSR  
WRSR  
READ  
WRITE  
00000110  
00000100  
00000101  
00000001  
00000011  
00000010  
00100000  
01100000  
Enable Write to UFM  
Disable Write to UFM  
Read Status Register  
Write Status Register  
Read data from UFM  
Write data to UFM  
Sector erase  
SECTOR-ERASE  
UFM-ERASE  
Erase the entire UFM block (both sectors)  
The READand WRITEopcodes are instructions for transmission, which means the data  
will be read from or written to the UFM.  
WREN, WRDI, RDSR, and WRSRare instructions for the status register, where they do not  
have any direct interaction with UFM, but read or set the status register within the  
interface logic. The status register provides status on whether the UFM block is  
available for any READor WRITEoperation, whether the interface is WRITEenabled, and  
the state of the UFM WRITEprotection. Table 7–11 lists the status register format. For  
the read only implementation of ALTUFMSPI (Base or Extended mode), the status  
register does not exist, saving LE resources.  
Table 7–11. Status Register Format  
Position  
Bit 7  
Status  
Default at Power-Up  
Description  
X
X
0
0
0
0
0
0
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
X
X
BP1  
BP0  
Indicate the current level of block write protection (1)  
Indicate the current level of block write protection (1)  
1= SPI WRITEenabled state  
Bit 1  
Bit 0  
WEN  
0
0
0= SPI WRITE disabled state  
1 = Busy, UFM WRITEor ERASEcycle in progress  
0 = No UFM WRITEor ERASEcycle in progress  
nRDY  
Note to Table 7–11:  
(1) For more information about status register bits BP1and BP0, refer to Table 7–12 and Table 7–13 on page 7–34  
.
The following sections describe the instructions for SPI.  
January 2011 Altera Corporation  
MAX V Device Handbook  
 复制成功!