欢迎访问ic37.com |
会员登录 免费注册
发布采购

5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
 浏览型号5M80ZE64I5N的Datasheet PDF文件第123页浏览型号5M80ZE64I5N的Datasheet PDF文件第124页浏览型号5M80ZE64I5N的Datasheet PDF文件第125页浏览型号5M80ZE64I5N的Datasheet PDF文件第126页浏览型号5M80ZE64I5N的Datasheet PDF文件第128页浏览型号5M80ZE64I5N的Datasheet PDF文件第129页浏览型号5M80ZE64I5N的Datasheet PDF文件第130页浏览型号5M80ZE64I5N的Datasheet PDF文件第131页  
Chapter 7: User Flash Memory in MAX V Devices  
7–23  
Software Support for UFM Block  
Instantiating the I2C Interface Using the Quartus II ALTUFM_I2C  
Megafunction  
Figure 7–19 shows the ALTUFM_I2C megafunction symbol for a I2C interface  
instantiation in the Quartus II software.  
Figure 7–19. ALTUFM_I2C Megafunction Symbol for the I2C Interface Instantiation in the Quartus  
II Software  
ALTUFM_I2C megafunction is under the Memory Compiler folder on page 2a of the  
MegaWizard Plug-In Manager. On page 3, you can choose whether to implement the  
Read/Write or Read Only mode for the UFM. You also have an option to choose the  
memory size for the ALTUFM_I2C megafunction as well as defining the four MSBs of  
the slave address (default 1010).  
You can select the optional write protection and erase operation methods on page 4 of  
the ALTUFM MegaWizard Plug-In Manager.  
1
The UFM block’s internal oscillator is always running when the ALTUFM_I2C  
megafunction is instantiated for both read-only and read/write interfaces.  
Serial Peripheral Interface  
Serial peripheral interface (SPI) is a four-pin serial communication subsystem  
included on the Motorola 6805 and 68HC11 series microcontrollers. It allows the  
microcontroller unit to communicate with peripheral devices, and is also capable of  
inter-processor communications in a multiple-master system.  
The SPI bus consists of masters and slaves. The master device initiates and controls  
the data transfers and provides the clock signal for synchronization. The slave device  
responds to the data transfer request from the master device. The master device in an  
SPI bus initiates a service request with the slave devices responding to the service  
request.  
With the ALTUFM megafunction, the UFM and MAX V logic can be configured as a  
slave device for the SPI bus. The OSC_ENAis always asserted to enable the internal  
oscillator when the SPI megafunction is instantiated for both read only and  
read/write interfaces.  
January 2011 Altera Corporation  
MAX V Device Handbook  
 复制成功!