Chapter 7: User Flash Memory in MAX V Devices
7–21
Software Support for UFM Block
Random Address Read
Random address read operation allows the master to select any byte location for a
read operation. The master first performs a “dummy” write operation by sending the
start condition, slave address, and byte address of the location it wishes to read. After
the ALTUFM_I2C megafunction acknowledges the slave and byte address, the master
generates a repeated start condition, the slave address, and the R/W bit is set to 1. The
ALTUFM_I2C megafunction then responds with acknowledge and sends the 8-bit
data requested. The master then generates a stop condition. Figure 7–16 shows the
random address read sequence.
Figure 7–16. Random Address Read Sequence
Slave
Address
Byte
Address
Slave
Address
Data
S
A
A
Sr
A
P
R/W
R/W
‘1’ (read)
‘0’ (write)
From Master to Slave
From Slave to Master
S – Start Condition
Sr – Repeated Start
P – Stop Condition
A – Acknowledge
Sequential Read
Sequential read operation can be initiated by either the current address read operation
or the random address read operation. Instead of sending a stop condition after the
slave has transmitted one byte of data to the master, the master acknowledges that
byte and sends additional clock pulses (on the SCL line) for the slave to transmit data
bytes from consecutive byte addresses. The operation is terminated when the master
generates a stop condition instead of responding with an acknowledge. Figure 7–17
shows the sequential read sequence.
Figure 7–17. Sequential Read Sequence
Slave
Address
Byte
Address
Slave
Address
Data
Data
S
A
A
Sr
A
A
P
R/W
R/W
…
‘1’ (read)
Data (n - bytes) + Acknowledgment (n - 1 bytes)
‘0’ (write)
From Master to Slave
From Slave to Master
S – Start Condition
Sr – Repeated Start
P – Stop Condition
A – Acknowledge
January 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
