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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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Chapter 7: User Flash Memory in MAX V Devices  
7–21  
Software Support for UFM Block  
Random Address Read  
Random address read operation allows the master to select any byte location for a  
read operation. The master first performs a “dummy” write operation by sending the  
start condition, slave address, and byte address of the location it wishes to read. After  
the ALTUFM_I2C megafunction acknowledges the slave and byte address, the master  
generates a repeated start condition, the slave address, and the R/W bit is set to 1. The  
ALTUFM_I2C megafunction then responds with acknowledge and sends the 8-bit  
data requested. The master then generates a stop condition. Figure 7–16 shows the  
random address read sequence.  
Figure 7–16. Random Address Read Sequence  
Slave  
Address  
Byte  
Address  
Slave  
Address  
Data  
S
A
A
Sr  
A
P
R/W  
R/W  
‘1’ (read)  
‘0’ (write)  
From Master to Slave  
From Slave to Master  
S – Start Condition  
Sr – Repeated Start  
P – Stop Condition  
A – Acknowledge  
Sequential Read  
Sequential read operation can be initiated by either the current address read operation  
or the random address read operation. Instead of sending a stop condition after the  
slave has transmitted one byte of data to the master, the master acknowledges that  
byte and sends additional clock pulses (on the SCL line) for the slave to transmit data  
bytes from consecutive byte addresses. The operation is terminated when the master  
generates a stop condition instead of responding with an acknowledge. Figure 7–17  
shows the sequential read sequence.  
Figure 7–17. Sequential Read Sequence  
Slave  
Address  
Byte  
Address  
Slave  
Address  
Data  
Data  
S
A
A
Sr  
A
A
P
R/W  
R/W  
‘1’ (read)  
Data (n - bytes) + Acknowledgment (n - 1 bytes)  
‘0’ (write)  
From Master to Slave  
From Slave to Master  
S – Start Condition  
Sr – Repeated Start  
P – Stop Condition  
A – Acknowledge  
January 2011 Altera Corporation  
MAX V Device Handbook  
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