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5M80ZE64I5N 参数 Datasheet PDF下载

5M80ZE64I5N图片预览
型号: 5M80ZE64I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, 64-Cell, CMOS, PQFP64, 9 X 9 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, EQFP-64]
分类和应用:
文件页数/大小: 166 页 / 4004 K
品牌: INTEL [ INTEL ]
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7–22  
Chapter 7: User Flash Memory in MAX V Devices  
Software Support for UFM Block  
ALTUFM_I2C Interface Timing Specification  
Figure 7–18 shows the timing waveform for the ALTUFM_I2C megafunction  
read/write mode.  
Figure 7–18. Timing Waveform for the ALTUFM_I2C Megafunction  
SDA  
t
t
SU:DAT  
HD:DAT  
t
t
t
HD:STA  
SU:STO  
SU:STA  
t
BUF  
t
SCLSDA  
t
SCL  
HIGH  
t
LOW  
Table 7–6 through Table 7–8 list the timing specification needed for the ALTUFM_I2C  
megafunction read/write mode.  
Table 7–6. I2C Interface Timing Specification  
Symbol Parameter  
FSCL SCL clock frequency  
tSCL:SDA  
tBUF  
Min  
4.7  
4
Max  
100  
15  
Unit  
kHz  
ns  
SCL going low to SDA data out  
Bus free time between a stop and start condition  
(Repeated) start condition hold time  
(Repeated) start condition setup time  
SCL clock low period  
µs  
tHD:STA  
tSU:STA  
tLOW  
µs  
4.7  
4.7  
4
µs  
µs  
tHIGH  
SCL clock high period  
µs  
tHD:DAT  
tSU:DAT  
tSU:STO  
SDA data in hold time  
0
ns  
SDA data in setup time  
20  
4
ns  
STOP condition setup time  
ns  
Table 7–7. UFM Write Cycle Time  
Parameter  
Min  
Max  
Unit  
Write Cycle Time  
110  
µs  
Table 7–8. UFM Erase Cycle Time  
Parameter  
Min  
Max  
Unit  
Sector Erase  
Cycle Time  
501  
ms  
Full Erase Cycle  
Time  
1,002  
ms  
MAX V Device Handbook  
January 2011 Altera Corporation  
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