7–22
Chapter 7: User Flash Memory in MAX V Devices
Software Support for UFM Block
ALTUFM_I2C Interface Timing Specification
Figure 7–18 shows the timing waveform for the ALTUFM_I2C megafunction
read/write mode.
Figure 7–18. Timing Waveform for the ALTUFM_I2C Megafunction
SDA
t
t
SU:DAT
HD:DAT
t
t
t
HD:STA
SU:STO
SU:STA
t
BUF
t
SCLSDA
t
SCL
HIGH
t
LOW
Table 7–6 through Table 7–8 list the timing specification needed for the ALTUFM_I2C
megafunction read/write mode.
Table 7–6. I2C Interface Timing Specification
Symbol Parameter
FSCL SCL clock frequency
tSCL:SDA
tBUF
Min
—
—
4.7
4
Max
100
15
Unit
kHz
ns
SCL going low to SDA data out
Bus free time between a stop and start condition
(Repeated) start condition hold time
(Repeated) start condition setup time
SCL clock low period
—
µs
tHD:STA
tSU:STA
tLOW
—
µs
4.7
4.7
4
—
µs
—
µs
tHIGH
SCL clock high period
—
µs
tHD:DAT
tSU:DAT
tSU:STO
SDA data in hold time
0
—
ns
SDA data in setup time
20
4
—
ns
STOP condition setup time
—
ns
Table 7–7. UFM Write Cycle Time
Parameter
Min
Max
Unit
Write Cycle Time
—
110
µs
Table 7–8. UFM Erase Cycle Time
Parameter
Min
Max
Unit
Sector Erase
Cycle Time
—
501
ms
Full Erase Cycle
Time
—
1,002
ms
MAX V Device Handbook
January 2011 Altera Corporation
INTEL [ INTEL ]
