Chapter 7: User Flash Memory in MAX V Devices
7–19
Software Support for UFM Block
Sector Erase (Byte Address Triggered)
This sector erase operation is triggered by defining a 7- to 10-bit byte address for each
sector depending on the memory size. The trigger address for each sector is entered
on page 4 of the ALTUFM MegaWizard Plug-In Manager. When a write operation is
executed targeting this special byte address location, the UFM sector that contains
that byte address location is erased. This sector erase operation is automatically
followed by a write of the intended write byte to that address. The default byte
address location for UFM Sector 0 erase is address 0×00. The default byte address
location for UFM Sector 1 erase is [(selected memory size)/2]. You can specify another
byte location as the trigger-erase addresses for each sector.
This sector erase operation supports up to eight UFM blocks or serial EEPROMs on
the I2C bus. This sector erase operation requires acknowledge polling.
Sector Erase (A2 Triggered)
This sector erase operation uses the received A2 slave address bit to distinguish
between an erase or read/write operation. This slave operation decoding occurs when
the master transmits the slave address after generating the start condition. If the A2 bit
received by the UFM slave is 1, the sector erase operation is selected. If the A2 bit
received is 0, the read/write operation is selected. While this reserves the A2 bit as an
erase or read/write operation bit, the A0 and A1 bits still act as slave address bits to
address the UFM. With this erase option, there can be up to four UFM slaves cascaded
on the bus for 1-Kbit and 2-Kbit memory sizes. Only two UFM slaves can be cascaded
on the bus for 4-Kbit memory size, because A0 of the slave address becomes the ninth
bit (MSB) of the byte address. After the slave acknowledges the slave address and its
erase or read/write operation bit, the master can transfer any byte address within the
sector that must be erased. The internal UFM sector erase operation only begins after
the master generates a stop condition. Figure 7–14 shows the sector erase sequence
using the A2 bit of the slave address.
Figure 7–14. Sector Erase Sequence Indicated Using the A2 Bit of the Slave Address
Slave Address
S
A
Byte Address
A
P
R/W
A
= '1'
2
(1)
'0' (write)
From Master to Slave
From Slave to Master
S – Start Condition
P – Stop Condition
A – Acknowledge
Note to Figure 7–14:
(1) A2 = 0 indicates a read/write operation is executed in place of an erase. Here, the R/W bit determines whether it is
a read or write operation.
If the ALTUFM_I2C megafunction is write-protected (WP=1), the slave does not
acknowledge the byte address (that indicates the UFM sector to be erased) sent in by
the master. The master should then send a stop condition to terminate the transfer and
the sector erase operation will not be executed.
January 2011 Altera Corporation
MAX V Device Handbook
INTEL [ INTEL ]
