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Configuration Specification
Configuration Specification
This section provides configuration specifications and timing for Cyclone V devices.
POR Specifications
Table 48 lists the specifications for fast and standard POR delay for Cyclone V devices.
Table 48. Fast and Standard POR Delay Specification for Cyclone V Devices (1)
POR Delay
Minimum
Maximum
12
Unit
ms
Fast (2)
4
Standard
100
300
ms
Notes to Table 48:
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Cyclone V
Devices” table in the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter.
(2) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize
after the POR trip.
JTAG Configuration Timing
Table 49 lists the JTAG timing parameters and values for Cyclone V devices.
Table 49. JTAG Timing Parameters and Values for Cyclone V Devices
Symbol
Description
Min
30
167 (1)
14
14
1
Max
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCP
tJCH
tJCL
TCK clock period
TCK clock period
TCK clock high time
TCK clock low time
tJPSU (TDI)
tJPSU (TMS)
tJPH
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
3
5
(2)
tJPCO
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
—
—
—
11
14
14
(2)
(2)
tJPZX
tJPXZ
Notes to Table 49:
(1) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile
key programming.
(2) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Cyclone V Device Datasheet
July 2014 Altera Corporation
INTEL [ INTEL ]
