Configuration Specification
Page 47
FPP Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Cyclone V devices.
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[] ratio when you turn on
encryption or the compression feature.
Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r
times the DATA[] rate in byte per second (Bps) or word per second (Wps). For
example, in FPP x16 where the r is 2, the DCLK frequency must be 2 times the DATA[]
rate in Wps.
Cyclone V devices use additional clock cycles to decrypt and decompress the
configuration data.
Table 50 lists the DCLK-to-DATA[] ratio for each combination.
Table 50. DCLK-to-DATA[] Ratio for Cyclone V Devices
Configuration Scheme
Encryption
Compression
DCLK-to-DATA[] ratio (r)
Off
On
Off
On
Off
On
Off
On
Off
Off
On
On
Off
Off
On
On
1
1
2
2
1
2
4
4
FPP (8-bit wide)
FPP (16-bit wide)
1
If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only
stop the DCLK DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into
the Cyclone V device.
(
July 2014 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
