CV-51002
2015.12.04
58
SD/MMC Timing Characteristics
SD/MMC Timing Characteristics
Table 45: Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices
After power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters the
Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum of 400
kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL setting. The
value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz.
After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of drvsel and smplsel via the system manager.
drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT increase
to a maximum of 200 MHz and 50 MHz respectively.
The SD/MMC interface calibration support will be available in a future release of the preloader through the SoC EDS software update.
Symbol
Description
Min
Max
Unit
SDMMC_CLK clock period
(Identification mode)
20
—
ns
Tsdmmc_clk (internal reference
clock)
SDMMC_CLK clock period
(Default speed mode)
5
5
—
—
—
—
—
55
ns
ns
ns
ns
ns
SDMMC_CLK clock period
(High speed mode)
SDMMC_CLK_OUT clock
period (Identification mode)
2500
40
Tsdmmc_clk_out (interface output
clock)
SDMMC_CLK_OUT clock
period (Default speed mode)
SDMMC_CLK_OUT clock
period (High speed mode)
20
Tdutycycle
Td
SDMMC_CLK_OUT duty cycle
45
%
SDMMC_CMD/SDMMC_D
output delay
(Tsdmmc_clk × drvsel)/2 (Tsdmmc_clk × drvsel)/2
ns
– 1.23 (69)
+ 1.69 (69)
(69)
drvsel is the drive clock phase shift select value.
Cyclone V Device Datasheet
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