CV-51002
2015.12.04
59
USB Timing Characteristics
Symbol
Description
Min
Max
Unit
Tsu
Th
Input setup time
1.05 – (Tsdmmc_clk
×
—
ns
smplsel)/2 (70)
Input hold time
(Tsdmmc_clk × smplsel)/
—
ns
2 (70)
Figure 8: SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tsu
Th
Command/Data In
Related Information
Booting and Configuration Chapter, Cyclone V Hard Processor System Technical Reference Manual
Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table.
USB Timing Characteristics
PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the
MicroChip USB3300 PHY device that has been proven to be successful on the development board.
Table 46: USB Timing Requirements for Cyclone V Devices
Symbol
Description
Min
—
Typ
16.67
—
Max
—
Unit
ns
Tclk
Td
USB CLK clock period
CLK to USB_STP/USB_DATA[7:0] output delay
4.4
11
ns
(70)
smplsel is the sample clock phase shift select value.
Cyclone V Device Datasheet
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