CV-51002
2015.12.04
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SPI Timing Characteristics
Figure 6: SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdinmax
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdinmax
Table 44: SPI Slave Timing Requirements for Cyclone V Devices
The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol
Description
Min
20
5
Max
—
—
—
—
—
6
Unit
ns
Tclk
Ts
CLK clock period
MOSI Setup time
MOSI Hold time
ns
Th
5
ns
Tsuss
Thss
Td
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid after last clock edge
Master-in slave-out (MISO) output delay
8
ns
8
ns
—
ns
Cyclone V Device Datasheet
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