CV-51002
2015.12.04
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Quad SPI Flash Timing Characteristics
Quad SPI Flash Timing Characteristics
Table 42: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices
Symbol
Description
Min
—
Typ
—
Max
108
—
Unit
MHz
ns
Fclk
SCLK_OUT clock frequency (External clock)
Tqspi_clk
QSPI_CLK clock period (Internal reference
clock)
2.32
—
Tdutycycle
Tdssfrst
SCLK_OUT duty cycle
45
—
—
55
—
%
Output delay QSPI_SS valid before first clock
edge
1/2 cycle of
SCLK_OUT
ns
Tdsslst
Output delay QSPI_SS valid after last clock
edge
–1
—
1
ns
Tdio
I/O data output delay
Input data valid start
–1
—
—
—
1
ns
ns
Tdin_start
(2 + Rdelay) ×
Tqspi_clk – 7.52 (68)
Tdin_end
Input data valid end
(2 + Rdelay) ×
—
—
ns
Tqspi_clk – 1.21 (68)
(68)
Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Altera provides automatic Quad
SPI calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Cyclone V Hard Processor
System Technical Reference Manual.
Cyclone V Device Datasheet
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