CV-51002
2015.12.04
55
SPI Timing Characteristics
Figure 5: Quad SPI Flash Timing Diagram
This timing diagram illustrates clock polarity mode 0 and clock phase mode 0.
Tdsslst
QSPI_SS
SCLK_OUT
QSPI_DATA
Tdssfrst
Tdio
Tdin_start
Data Out
Data In
Tdin_end
Related Information
Quad SPI Flash Controller Chapter, Cyclone V Hard Processor System Technical Reference Manual
Provides more information about Rdelay.
SPI Timing Characteristics
Table 43: SPI Master Timing Requirements for Cyclone V Devices
The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol
Description
Min
16.67
45
Max
—
Unit
ns
%
Tclk
CLK clock period
Tdutycycle
Tdssfrst
Tdsslst
SPI_CLK duty cycle
55
—
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid after last clock edge
Master-out slave-in (MOSI) output delay
8
ns
ns
ns
ns
8
—
Tdio
–1
1
Tdinmax
Maximum data input delay from falling edge of SPI_CLK to data
arrival at SoC. The RX sample delay register can be programmed to
control the capture of input data.
—
500
Cyclone V Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
