CV-51002
2015.12.04
52
Duty Cycle Distortion (DCD) Specifications
Duty Cycle Distortion (DCD) Specifications
Table 38: Worst-Case DCD on Cyclone V I/O Pins
The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD.
–C6
–C7, –I7
–C8, –A7
Symbol
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
HPS Specifications
This section provides HPS specifications and timing for Cyclone V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of
HPS_CLK1.
HPS Clock Performance
Table 39: HPS Clock Performance for Cyclone V Devices
Symbol/Description
mpu_base_clk (microprocessor unit clock)
main_base_clk (L3/L4 interconnect clock)
h2f_user0_clk
–C6
–C7, –I7
800
–A7
700
350
100
100
160
–C8
600
300
100
100
160
Unit
925
400
100
100
200
MHz
MHz
MHz
MHz
MHz
400
100
h2f_user1_clk
100
h2f_user2_clk
200
Cyclone V Device Datasheet
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