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2015.12.04
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HPS PLL Specifications
HPS PLL Specifications
HPS PLL VCO Frequency Range
Table 40: HPS PLL VCO Frequency Range for Cyclone V Devices
Description
Speed Grade
–C7, –I7, –A7, –C8
–C6
Minimum
320
Maximum
1,600
Unit
MHz
MHz
VCO range
320
1,850
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.
Related Information
Clock Select, Booting and Configuration chapter
Provides more information about the clock range for different values of clock select (CSEL).
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value
programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the
denominator is 1 to 64.
Maximum input jitter = Input clock period × Divide value (N) × 0.02
Table 41: Examples of Maximum Input Jitter
Input Reference Clock Period
Divide Value (N)
Maximum Jitter
Unit
ns
40 ns
40 ns
40 ns
1
2
4
0.8
1.6
3.2
ns
ns
Cyclone V Device Datasheet
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