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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
51  
OCT Calibration Block Specifications  
OCT Calibration Block Specifications  
Table 37: OCT Calibration Block Specifications for Cyclone V Devices  
Symbol  
OCTUSRCLK  
TOCTCAL  
Description  
Min  
Typ  
Max  
20  
Unit  
Clock required by OCT calibration blocks  
MHz  
Cycles  
Number of OCTUSRCLK clock cycles required for RS  
1000  
OCT/RT OCT calibration  
TOCTSHIFT  
TRS_RT  
Number of OCTUSRCLK clock cycles required for OCT  
32  
Cycles  
ns  
code to shift out  
Time required between the dyn_term_ctrl and oe  
signal transitions in a bidirectional I/O buffer to  
dynamically switch between RS OCT and RT OCT  
2.5  
Figure 4: Timing Diagram for oe and dyn_term_ctrl Signals  
Tristate  
TX  
Tristate  
RX  
RX  
oe  
dyn_term_ctrl  
TRS_RT  
TRS_RT  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
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