CV-51002
2015.12.04
50
DLL Frequency Range Specifications
DLL Frequency Range Specifications
Table 34: DLL Frequency Range Specifications for Cyclone V Devices
Parameter
–C6
–C7, –I7
–C8
Unit
DLL operating frequency range
167 – 400
167 – 400
167 – 333
MHz
DQS Logic Block Specifications
Table 35: DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V Devices
This error specification is the absolute maximum and minimum error.
Number of DQS Delay Buffer
–C6
–C7, –I7
–C8
Unit
2
40
80
80
ps
Memory Output Clock Jitter Specifications
Table 36: Memory Output Clock Jitter Specifications for Cyclone V Devices
The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.
–C6
–C7, –I7
–C8
Parameter
Clock Network
Symbol
Unit
Min
–60
—
Max
60
Min
–70
—
Max
70
Min
–70
—
Max
70
Clock period jitter
PHYCLK
PHYCLK
tJIT(per)
tJIT(cc)
ps
ps
Cycle-to-cycle period jitter
90
100
100
Cyclone V Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
