CV-51002
2015.12.04
47
High-Speed I/O Specifications
–C8, –A7
–C6
Typ
—
–C7, –I7
Typ
Symbol
Condition
Unit
Min
Max
Min
Max
Min
Typ
Max
(65)
(66)
(65)
(66)
(65)
(66)
SERDES
factor J = 1 to
2, uses DDR
registers
—
—
Mbps
(65)
(65)
(65)
Emulated Differential I/O
Standards with Three
SERDES
factor J = 4 to
10
—
640
—
640
—
550
Mbps
External Output Resistor
Networks- fHSDR (data rate)
(67)
(65)
(65)
(65)
Emulated Differential I/O
Standards with One
SERDES
factor J = 4 to
10
—
—
170
350
—
—
170
380
—
—
170
500
Mbps
ps
External Output Resistor
Network - fHSDR (data rate)
Total Jitterfor
Data Rate, 600
Mbps – 840
Mbps
—
—
—
tx Jitter -True Differential I/O
Standards(67)
Total Jitter for
Data Rate <
600Mbps
—
—
—
—
0.21
500
—
—
—
—
0.23
500
—
—
—
—
0.30
500
UI
ps
tx Jitter -Emulated
Differential I/O
Total Jitter for
Data Rate <
640Mbps
Standards with Three
External Output Resistor
Networks
(66)
The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (fout), provided you can close the design timing and the signal
integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the
board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(67)
Cyclone V Device Datasheet
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