AV-51002
2015.12.16
2-59
FPP Configuration Timing when DCLK to DATA[] = 1
FPP Configuration Timing when DCLK to DATA[] = 1
Figure 2-7: FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
Timing waveform for FPP configuration when using a MAX® II or MAX V device as an external host.
t
CF2ST1
t
CFG
t
CF2CK
nCONFIG
nSTATUS (2)
t
STATUS
(6)
t
CF2ST0
t
CLK
CONF_DONE (3)
t
CH
t
CL
t
CF2CD
t
ST2CK
(4)
DCLK
t
DH
Word 0 Word 1 Word 2 Word 3
Word n-2 Word n-1
DATA[31..0](5)
User Mode
User Mode
t
DSU
User I/O
High-Z
(7)
INIT_DONE
t
CD2UM
Notes:
1. The beginning of this waveform shows the device in user mode. In user mode,
nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is
pulled low, a reconfiguration cycle begins.
2. After power-up, the Arria V GZ device holds nSTATUS low for the time of the POR delay.
3. After power-up, before and during configuration, CONF_DONE is low.
4. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete.
It can toggle high or low if required.
5. For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0] are available as a user I/O
pin after configuration. The state of this pin depends on the dual-purpose pin settings.
6. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device.
CONF_DONE is released high when the Arria V GZ device receives all the configuration data
successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
7. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE
goes low.
Arria V GZ Device Datasheet
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