AV-51002
2015.12.16
2-56
Configuration Specification
Configuration Specification
POR Specifications
Table 2-53: Fast and Standard POR Delay Specification for Arria V GZ Devices
Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices” table in the Configuration, Design
Security, and Remote System Upgrades in Arria V Devices chapter.
POR Delay
Minimum (ms)
Maximum (ms)
Fast
Standard
4
12 (201)
100
300
Related Information
Configuration, Design Security, and Remote System Upgrades in Arria V Devices
JTAG Configuration Specifications
Table 2-54: JTAG Timing Parameters and Values for Arria V GZ Devices
Symbol
Description
Min
Max
—
Unit
ns
tJCP
tJCP
tJCH
tJCL
TCK clock period
30
TCK clock period
167 (202)
—
ns
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
14
14
2
—
ns
—
ns
tJPSU (TDI)
tJPSU (TMS)
—
ns
3
—
ns
(201)
(202)
The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip.
The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile key programming.
Arria V GZ Device Datasheet
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