AV-51002
2015.12.16
2-57
Fast Passive Parallel (FPP) Configuration Timing
Symbol
Description
Min
5
Max
—
Unit
ns
tJPH
JTAG port hold time
tJPCO
tJPZX
tJPXZ
JTAG port clock to output
—
—
—
11 (203)
14 (203)
14 (203)
ns
JTAG port high impedance to valid output
JTAG port valid output to high impedance
ns
ns
Fast Passive Parallel (FPP) Configuration Timing
DCLK-to-DATA[] Ratio (r) for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[]ratio when you turn on encryption or the compression feature.
Table 2-55: DCLK-to-DATA[] Ratio for Arria V GZ Devices
Depending on the DCLK-to-DATA[]ratio, the host must send a DCLKfrequency that is r times the data rate in bytes per second (Bps), or words per second
(Wps). For example, in FPP ×16 when the DCLK-to-DATA[]ratio is 2, the DCLKfrequency must be 2 times the data rate in Wps. Arria V GZ devices use the
additional clock cycles to decrypt and decompress the configuration data.
Configuration Scheme
Decompression
Disabled
Disabled
Enabled
Design Security
Disabled
Enabled
DCLK-to-DATA[] Ratio
1
1
2
2
1
2
4
4
FPP ×8
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
FPP ×16
Disabled
Enabled
Enabled
(203)
A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO I/O bank = 2.5 V, or 13 ns if it
equals 1.8 V.
Arria V GZ Device Datasheet
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