AV-51002
2015.12.16
2-62
FPP Configuration Timing when DCLK to DATA[] > 1
FPP Configuration Timing when DCLK to DATA[] > 1
Figure 2-8: FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 ,
Timing when using a MAX II device, MAX V device, or microprocessor as an external host.
t
CF2ST1
t
CFG
t
nCONFIG
CF2CK
nSTATUS (3)
t
STATUS
t
CF2ST0
CONF_DONE (4)
t
CH
CL
t
CF2CD
(8)
t
ST2CK
t
DCLK (6)
DATA[31..0] (8)
User I/O
(7)
(5)
1
2
1
1
2
r
1
2
r
r
t
CLK
Word 0
Word 1
Word (n-1)
User Mode
User Mode
Word 3
t
DH
t
t
DH
DSU
High-Z
(9)
INIT_DONE
t
CD2UM
Notes:
1. To find out the DCLK-to-DATA[] ratio for your system, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table.
2. The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
3. After power-up, the Arria V GZ device holds nSTATUS low for the time as specified by the POR delay.
4. After power-up, before and during configuration, CONF_DONE is low.
5. Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or
low if required.
6. “r”denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design
security feature enable settings, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table.
7. If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0]
pins prior to sending the first DCLK rising edge.
8. To ensure a successful configuration, send the entire configuration data to the Arria V GZ device. CONF_DONE is
released high after the Arria V GZ device receives all the configuration data successfully. After CONF_DONE goes
high, send two additional falling edges on DCLK to begin initialization and enter user mode.
9. After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Arria V GZ Device Datasheet
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