AV-51002
2015.12.16
2-55
Duty Cycle Distortion (DCD) Specifications
Symbol
TOCTSHIFT
TRS_RT
Description
Min
—
Typ
32
Max
—
Unit
Cycles
ns
Number of OCTUSRCLK clock cycles required for the OCT code to shift out
Time required between the dyn_term_ctrland oesignal transitions in a
bidirectional I/O buffer to dynamically switch between OCT RS and RT (See
the figure below.)
—
2.5
—
Figure 2-6: Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
Tristate
RX
oe
dyn_term_ctrl
TX
RX
T
T
RS_RT
RS_RT
Duty Cycle Distortion (DCD) Specifications
Table 2-52: Worst-Case DCD on Arria V GZ I/O Pins
The DCD numbers do not cover the core clock network.
C3, I3L
C4, I4
Symbol
Unit
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
%
Arria V GZ Device Datasheet
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