AV-51002
2015.12.16
2-60
FPP Configuration Timing when DCLK to DATA[] = 1
Note: When you enable the decompression or design security feature, the DCLK-to-DATA[]ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the
respective DCLK-to-DATA[]ratio, refer to the "DCLK-to-DATA[] Ratio for Arria V GZ Devices" table.
Table 2-56: FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is 1
Use these timing parameters when the decompression and design security features are disabled.
Symbol
Parameter
Minimum
Maximum
600
Unit
ns
ns
μs
tCF2CD nCONFIGlow to CONF_DONElow
tCF2ST0 nCONFIGlow to nSTATUSlow
—
—
600
tCFG
nCONFIGlow pulse width
2
—
tSTATUS nSTATUSlow pulse width
268
—
1,506 (204)
1,506 (205)
—
μs
tCF2ST1 nCONFIGhigh to nSTATUShigh
μs
tCF2CK nCONFIGhigh to first rising edge on DCLK
1,506
μs
(206)
(206)
tST2CK nSTATUShigh to first rising edge of DCLK
2
—
—
μs
ns
tDSU
tDH
tCH
tCL
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLKhigh time
5.5
0
0.45 × 1/fMAX
0.45 × 1/fMAX
1/fMAX
—
—
ns
—
s
DCLKlow time
—
s
tCLK
DCLK period
—
s
DCLKfrequency (FPP ×8/×16)
DCLKfrequency (FPP ×32)
tCD2UM CONF_DONEhigh to user mode (207)
125
100
437
MHz
MHz
μs
fMAX
—
175
(204)
(205)
(206)
(207)
This value is applicable if you do not delay configuration by extending the nCONFIGor nSTATUSlow pulse width.
This value is applicable if you do not delay configuration by externally holding the nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
Arria V GZ Device Datasheet
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