AV-51002
2015.12.16
2-63
FPP Configuration Timing when DCLK to DATA[] > 1
Table 2-57: FPP Timing Parameters for Arria V GZ Devices When the DCLK-to-DATA[] Ratio is >1
Use these timing parameters when you use the decompression and design security features.
Symbol
Parameter
Minimum
Maximum
Unit
tCF2CD
tCF2ST0
tCFG
tSTATUS
tCF2ST1
nCONFIGlow to CONF_DONElow
—
600
600
—
ns
ns
μs
μs
μs
μs
μs
ns
s
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
nSTATUSlow pulse width
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATA[] setup time before rising edge on DCLK
DATA[] hold time after rising edge on DCLK
DCLKhigh time
—
2
268
1,506 (209)
1,506 (210)
—
—
(211)
tCF2CK
1,506
2
(211)
tST2CK
tDSU
tDH
—
5.5
—
(212)
N–1/fDCLK
—
tCH
0.45 × 1/fMAX
—
s
tCL
DCLKlow time
0.45 × 1/fMAX
—
s
tCLK
DCLKperiod
1/fMAX
—
—
s
DCLKfrequency (FPP ×8/×16)
DCLKfrequency (FPP ×32)
Input rise time
125
100
40
MHz
MHz
ns
ns
fMAX
—
tR
tF
—
Input fall time
—
40
(209)
(210)
(211)
(212)
You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
You can obtain this value if you do not delay configuration by externally holding the nSTATUSlow.
If nSTATUSis monitored, follow the tST2CK specification. If nSTATUSis not monitored, follow the tCF2CK specification.
N is the DCLK-to-DATAratio and fDCLK is the DCLKfrequency the system is operating.
Arria V GZ Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
