AV-51002
2015.12.16
1-51
High-Speed I/O Specifications
–C6
–I3, –C4
Typ
–I5, –C5
Typ
Symbol
Condition
Unit
Min
Max
Min
Max
Min
Typ
Max
(77)
(77)
(77)
SERDES factor J ≥
8(76)(78), LVDS TX with
RX DPA
—
1600
—
1500
—
1250
Mbps
Mbps
Mbps
(77)
(77)
(79)
(77)
(77)
(79)
(77)
(77)
(79)
SERDES factor J = 1
to 2, Uses DDR
Registers
—
—
—
—
—
—
Emulated Differential I/
O Standards with Three
External Output Resistor
Network - fHSDR (data
rate)(80)
SERDES factor J = 4
to 10(81)
945
945
945
(77)
(77)
(77)
Emulated Differential I/
O Standards with One
External Output Resistor
Network - fHSDR (data
rate)(80)
SERDES factor J = 4
to 10(81)
—
200
—
200
—
200
Mbps
Total Jitter for Data
Rate 600 Mbps – 1.25
Gbps
—
—
—
—
160
0.1
—
—
—
—
160
0.1
—
—
—
—
160
0.1
ps
tx Jitter -True Differential
I/O Standards
Total Jitter for Data
Rate < 600 Mbps
UI
(78)
The VCC and VCCP must be on a separate power layer and a maximum load of 5 pF for chip-to-chip interface.
(79)
(80)
(81)
The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT), provided you can close the design timing and
the signal integrity simulation is clean.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin,
transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
Arria V GX, GT, SX, and ST Device Datasheet
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