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5AGXMA1D4F27I5N 参数 Datasheet PDF下载

5AGXMA1D4F27I5N图片预览
型号: 5AGXMA1D4F27I5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-53  
High-Speed I/O Specifications  
–C6  
–I3, –C4  
Typ  
–I5, –C5  
Typ  
Symbol  
Condition  
Unit  
Min  
Max  
Min  
Max  
Min  
Typ  
Max  
True Differential I/O  
Standards  
150  
150  
150  
ps  
TCCS  
Emulated Differential  
I/O Standards  
300  
300  
300  
ps  
SERDES factor J =3 to 150  
10(76)  
1250  
150  
1250  
150  
1050  
Mbps  
Mbps  
Mbps  
Mbps  
True Differential I/O  
Standards - fHSDRDPA  
(data rate)  
SERDES factor J ≥ 8  
with DPA(76)(78)  
150  
1600  
150  
1500  
150  
1250  
(77)  
(83)  
(77)  
(83)  
(77)  
(83)  
Receiver  
SERDES factor J = 3  
to 10  
(77)  
(79)  
(77)  
(79)  
(77)  
(79)  
fHSDR (data rate)  
SERDES factor J = 1  
to 2, uses DDR  
registers  
DPA Mode DPA run length  
10000  
300  
10000  
300  
10000  
300  
UI  
Soft-CDR  
Mode  
Soft-CDR ppm tolerance  
ppm  
Non-DPA  
Mode  
Sampling Window  
300  
300  
300  
ps  
(83)  
You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board  
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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