AV-51002
2015.12.16
1-47
PLL Specifications
Unit
Symbol
Parameter
Condition
Min
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
Max
600
60
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
ps (p-p)
Cycle-to-cycle jitter for clock output on
a regular I/O in integer PLL
(67)(70)
tOUTCCJ_IO
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
600
60
Cycle-to-cycle jitter for clock output on
a regular I/O in fractional PLL
(67)(68)(70)
(67)(71)
tFOUTCCJ_IO
175
17.5
10
Period jitter for dedicated clock output
in cascaded PLLs
tCASC_OUTPJ_DC
tDRIFT
Frequency drift after PFDENAis disabled
for a duration of 100 µs
dKBIT
Bit number of Delta Sigma Modulator
(DSM)
—
8
24
32
bits
kVALUE
fRES
Numerator of fraction
—
128
8388608
5.96
2147483648
0.023
—
Resolution of VCO frequency
fINPFD = 100 MHz
390625
Hz
Related Information
Memory Output Clock Jitter Specifications on page 1-57
Provides more information about the external memory interface clock output jitter specifications.
(71)
The cascaded PLL specification is only applicable with the following conditions:
• Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
• Downstream PLL: Downstream PLL BW > 2 MHz
Arria V GX, GT, SX, and ST Device Datasheet
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