AV-51002
2015.12.16
1-50
High-Speed I/O Specifications
High-Speed I/O Specifications
Table 1-40: High-Speed I/O Specifications for Arria V Devices
When J = 3 to 10, use the serializer/deserializer (SERDES) block. When J = 1 or 2, bypass the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
The Arria V devices support the following output standards using true LVDS output buffer types on all I/O banks.
• True RSDS output standard with data rates of up to 360 Mbps
• True mini-LVDS output standard with data rates of up to 400 Mbps
–I3, –C4
Typ
–I5, –C5
Typ
–C6
Typ
—
Symbol
Condition
Unit
Min
Max
Min
Max
Min
Max
fHSCLK_in (input clock frequency) True Clock boost factor W
5
—
800
5
—
750
5
625
MHz
MHz
MHz
Differential I/O Standards
= 1 to 40(72)
fHSCLK_in (input clock frequency)
Single-Ended I/O Standards(73)
Clock boost factor W
= 1 to 40(72)
5
5
—
—
625
420
5
5
—
—
625
420
5
5
—
—
500
420
fHSCLK_in (input clock frequency)
Single-Ended I/O Standards(74)
Clock boost factor W
= 1 to 40(72)
fHSCLK_OUT (output clock frequency)
—
5
(77)
—
—
625(75)
1250
5
(77)
—
—
625(75)
1250
5
(77)
—
—
500(75)
1050
MHz
True Differential I/O
Transmitter Standards - fHSDR (data
rate)
SERDES factor J =3 to
10(76)
Mbps
(72)
(73)
(74)
(75)
(76)
Clock boost factor (W) is the ratio between the input data rate and the input clock rate.
This applies to DPA and soft-CDR modes only.
This applies to non-DPA mode only.
This is achieved by using the LVDS clock network.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design
dependent and requires timing analysis.
(77)
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
Arria V GX, GT, SX, and ST Device Datasheet
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