AV-51002
2015.12.16
1-48
DSP Block Performance Specifications
DSP Block Performance Specifications
Table 1-37: DSP Block Performance Specifications for Arria V Devices
Performance
–I5, –C5
310
Mode
Unit
–I3, –C4
370
–C6
220
220
220
220
200
220
220
Independent 9 × 9 multiplication
Independent 18 × 19 multiplication
Independent 18 × 25 multiplication
MHz
MHz
MHz
MHz
MHz
MHz
MHz
370
310
370
310
Modes using One
DSP Block
Independent 20 × 24 multiplication
Independent 27 × 27 multiplication
Two 18 × 19 multiplier adder mode
370
310
310
250
370
310
18 × 18 multiplier added summed with 36-
bit input
370
310
Modes using Two
DSP Blocks
Complex 18 × 19 multiplication
370
310
220
MHz
Memory Block Performance Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX
.
Arria V GX, GT, SX, and ST Device Datasheet
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