AV-51002
2015.12.16
1-54
DPA Lock Time Specifications
DPA Lock Time Specifications
Figure 1-4: Dynamic Phase Alignment (DPA) Lock Time Specifications with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 Data
96 Slow
256 Data
96 Slow
256 Data
Transitions
Clock Cycles
Transitions
Clock Cycles
Transitions
Table 1-41: DPA Lock Time Specifications for Arria V Devices
The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1
or 1-to-0 transition.
Standard
Training Pattern
Number of Data
Transitions in One
Repetition of the Training
Pattern
Number of Repetitions per
Maximum Data Transition
256 Data Transitions(84)
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640
640
640
640
640
Parallel Rapid I/O
Miscellaneous
10010000
10101010
32
01010101
32
(84)
This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Arria V GX, GT, SX, and ST Device Datasheet
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