Processor Configuration Registers
2.5.38
CAPID0_A—Capabilities A Register
This register control of bits in this register are only required for customer visible SKU
differentiation.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
E4–E7h
00000000h
RO-FW, RO-KFW
32 bits
Size:
BIOS Optimal Default:
000000h
Reset
Value
RST/
PWR
Bit
Access
Description
31
30
29
28
27
26
25
24
RO-KFW
RO-KFW
RO-KFW
RO-KFW
RO-FW
RO-FW
RO-FW
RO-FW
0b
0b
0b
0b
0b
0b
0b
0b
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved
Uncore
Uncore
Reserved (RSVD)
VTd Disable (VTDD)
0 = Enable VTd
23
RO-KFW
0b
1 = Disable VTd
22
21
RO-FW
RO-FW
RO-FW
RO-FW
RO-FW
RO-FW
RO-KFW
0b
0b
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
20:19
18
00b
0b
17
0b
16
0b
15
0b
2 DIMMS per Channel Disable (DDPCD)
This bit allows Dual Channel operation but only supports 1
DIMM per channel.
0 = 2 DIMMs per channel enabled
14
RO-FW
0b
Uncore
1 = 2 DIMMs per channel disabled. This setting hardwires
bits 2 and 3 of the rank population field for each channel
to zero. (MCHBAR offset 260h, bits 22:23 for channel 0
and MCHBAR offset 660h, bits 22:23 for channel 1)
13
12
RO-FW
RO-FW
RO-KFW
RO-FW
RO-FW
RO-FW
0b
0b
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
11
0b
10
0b
9:8
7:4
00b
0h
82
Datasheet, Volume 2
INTEL [ INTEL ]
