Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
BC–BFh
00100000h
RW-KL, RW-L
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
Top of Low Usable DRAM (TOLUD)
This register contains bits 31:20 of an address one byte above
the maximum DRAM memory below 4 GB that is usable by the
operating system. Address bits 31:20 programmed to 01h
implies a minimum memory size of 1 MB. Configuration software
must set this value to the smaller of the following 2 choices:
maximum amount memory in the system minus Intel ME stolen
memory plus one byte or the minimum address allocated for PCI
memory. Address bits 19:0 are assumed to be 0_0000h for the
purposes of address comparison. The Host interface positively
decodes an address towards DRAM if the incoming address is less
than the value programmed in this register.
31:20
RW-L
001h
Uncore
The Top of Low Usable DRAM is the lowest address above both
Graphics Stolen memory and TSEG. BIOS determines the base of
Graphics Stolen Memory by subtracting the Graphics Stolen
Memory Size from TOLUD and further decrements by TSEG size
to determine base of TSEG. All the Bits in this register are locked
in Intel TXT mode.
This register must be 1 MB aligned when reclaim is enabled.
19:1
0
RO
0h
0b
Reserved (RSVD)
Lock (LOCK):
RW-KL
Uncore
This bit will lock all writeable settings in this register, including
itself.
2.5.37
SKPD—Scratchpad Data Register
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
DC–DFh
00000000h
RW
Size:
32 bits
Reset
Value
RST/
PWR
Bit
Access
Description
Scratchpad Data (SKPD)
1 DWord of data storage.
31:0
RW
00000000h
Uncore
Datasheet, Volume 2
81
INTEL [ INTEL ]
