Processor Configuration Registers
2.5.32
TOUUD—Top of Upper Usable DRAM Register
This 64 bit register defines the Top of Upper Usable DRAM.
Configuration software must set this value to TOM minus all Intel ME stolen memory if
reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit +
1 byte, 1 MB aligned, since reclaim limit is 1 MB aligned. Address bits 19:0 are
assumed to be 000_0000h for the purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the incoming address is less than the
value programmed in this register and greater than or equal to 4 GB.
BIOS Restriction: Minimum value for TOUUD is 4 GB.
These bits are Intel TXT lockable.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
A8–AFh
0000000000000000h
RW-KL, RW-L
64 bits
Size:
BIOS Optimal Default
00000000000h
Reset
Value
RST/
PWR
Bit
Access
Description
63:39
RO
0h
Reserved (RSVD)
TOUUD (TOUUD)
This register contains bits 38:20 of an address one byte above
the maximum DRAM memory above 4 GB that is usable by the
operating system. Configuration software must set this value to
TOM minus all Intel ME stolen memory if reclaim is disabled. If
reclaim is enabled, this value must be set to reclaim limit 1 MB
aligned since reclaim limit + 1byte is 1 MB aligned. Address bits
19:0 are assumed to be 000_0000h for the purposes of address
comparison. The Host interface positively decodes an address
towards DRAM if the incoming address is less than the value
programmed in this register and greater than 4 GB.
38:20
RW-L
00000h
Uncore
All the bits in this register are locked in Intel TXT mode.
19:1
0
RO
0h
0b
Reserved (RSVD)
Lock (LOCK)
RW-KL
Uncore
This bit will lock all writeable settings in this register, including
itself.
78
Datasheet, Volume 2
INTEL [ INTEL ]
