Processor Configuration Registers
2.5.33
BDSM—Base Data of Stolen Memory Register
This register contains the base address of graphics data stolen DRAM memory. BIOS
determines the base of graphics data stolen memory by subtracting the graphics data
stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset
BCh bits 31:20).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
B0–B3h
00000000h
RW-KL, RW-L
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
Graphics Base of Stolen Memory (BDSM):
This register contains bits 31:20 of the base address of stolen
DRAM memory. BIOS determines the base of graphics stolen
memory by subtracting the graphics stolen memory size (PCI
Device 0 offset 52 bits 6:4) from TOLUD (PCI Device 0 offset BCh
bits 31:20).
31:20
RW-L
000h
Uncore
Uncore
19:1
0
RO
0h
0b
Reserved (RSVD)
Lock (LOCK)
RW-KL
This bit will lock all writeable settings in this register, including
itself.
2.5.34
BGSM—Base of GTT Stolen Memory Register
This register contains the base address of stolen DRAM memory for the GTT. BIOS
determines the base of GTT stolen memory by subtracting the GTT graphics stolen
memory size (PCI Device 0 offset 52h bits 9:8) from the Graphics Base of Data Stolen
Memory (PCI Device 0 offset B0h bits 31:20).
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
B4–B7h
00100000h
RW-L, RW-KL
32 bits
Size:
BIOS Optimal Default
00000h
Reset
Value
RST/
PWR
Bit
Access
Description
Graphics Base of GTT Stolen Memory (BGSM)
This register contains the base address of stolen DRAM memory
for the GTT. BIOS determines the base of GTT stolen memory by
subtracting the GTT graphics stolen memory size (PCI Device 0
offset 52h bits 11:8) from the Graphics Base of Data Stolen
Memory (PCI Device 0 offset B0h bits 31:20).
31:20
RW-L
001h
Uncore
Uncore
19:1
0
RO
0h
0b
Reserved (RSVD)
Lock (LOCK)
RW-KL
This bit will lock all writeable settings in this register, including
itself.
Datasheet, Volume 2
79
INTEL [ INTEL ]
