Processor Configuration Registers
B/D/F/Type:
Address Offset:
Default Value:
Access:
0/0/0/PCI
E8-EBh
00100000h
RO-FW, RO-KFW
32 bits
Size:
BIOS Optimal Default:
Bit Access
11 RO-FW
000000h
RST/
PWR
Reset Value
Description
0b
000b
0b
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
10:8
7
RO-FW
RO-FW
DDR3 Maximum Frequency Capability (DMFC)
PCODE will update this field with the value of FUSE_DMFC,
and then apply SSKU overrides.
Maximum allowed memory frequency with 133 MHz reference
clock.
This is a reversed 3-bit field:
7 = Up to DDR-1066 (4 x 266)
6 = Up to DDR-1333 (5 x 266)
5 = Up to DDR-1600 (6 x 266)
4 = Up to DDR-1866 (7 x 266)
3 = Up to DDR-2133 (8 x 266)
2 = Up to DDR-2400 (9 x 266)
1 = Up to DDR-2666 (10 x 266)
6:4
RO-FW
000b
Uncore
0 = Up to DDR-2933 (11 x 266) -- reserved fuse value; not
really supported;
3
2
1
0
RO-FW
RO-FW
RO-FW
RO-FW
0b
0b
0b
0b
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Reserved (RSVD)
Datasheet, Volume 2
85
INTEL [ INTEL ]
