Processor Configuration Registers
2.6
PCI Device 1 Function 0–2 Configuration Space
Registers
Table 2-9.
PCI Device 1 Function 0–2 Configuration Space Register Address Map (Sheet 1
of 2)
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–1h
2–3h
4–5h
6–7h
VID
DID
Vendor Identification
8086h
0151h
0000h
RO
Device Identification
PCI Command
PCI Status
RO-FW
RO, RW
PCICMD
PCISTS
RO, RW1C,
RO-V
0010h
8h
RID
CC
Revision Identification
Class Code
00h
060400h
00h
RO-FW
RO
9–Bh
Ch
CL
Cache Line Size
RW
Dh
RSVD
Reserved
0h
RO
Eh
HDR
Header Type
81h
RO
F–17h
18h
RSVD
Reserved
0h
RO
PBUSN
SBUSN
SUBUSN
RSVD
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reserved
00h
RO
19h
00h
RW
1Ah
00h
RW
1Bh
0h
RO
1Ch
IOBASE
IOLIMIT
SSTS
I/O Base Address
F0h
RW
1Dh
I/O Limit Address
00h
RW
1E–1Fh
20–21h
22–23h
24–25h
26–27h
28–2Bh
2C–2Fh
30–33h
34h
Secondary Status
0000h
FFF0h
0000h
FFF1h
0001h
00000000h
00000000h
0h
RW1C, RO
RW
MBASE
MLIMIT
PMBASE
PMLIMIT
PMBASEU
PMLIMITU
RSVD
Memory Base Address
Memory Limit Address
Prefetchable Memory Base Address
Prefetchable Memory Limit Address
Prefetchable Memory Base Address Upper
Prefetchable Memory Limit Address Upper
Reserved
RW
RO, RW
RW, RO
RW
RW
RO
CAPPTR
RSVD
Capabilities Pointer
88h
RO
35–3Bh
3Ch
Reserved
0h
RO
INTRLINE
INTRPIN
BCTRL
RSVD
Interrupt Line
00h
RW
3Dh
Interrupt Pin
01h
RW-O, RO
RO, RW
RO
3E–3Fh
40–7Fh
80–83h
84–87h
88–8Bh
8C–8Fh
90–91h
Bridge Control
0000h
0h
Reserved
PM_CAPID
PM_CS
SS_CAPID
SS
Power Management Capabilities
Power Management Control/Status
Subsystem ID and Vendor ID Capabilities
Subsystem ID and Subsystem Vendor ID
Message Signaled Interrupts Capability ID
C8039001h
00000008h
0000800Dh
00008086h
A005h
RO, RO-V
RO, RW
RO
RW-O
RO
MSI_CAPID
86
Datasheet, Volume 2
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