Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
87h
00h
RW
8 bits
0h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
PEG10 MDA Present (MDAP10)
This bit works with the VGA Enable bits in the BCTRL register of
Device 1 Function 0 to control the routing of processor initiated
transactions targeting MDA compatible I/O and memory address
ranges. This bit should not be set if Device 1 Function 0 VGA
Enable bit is not set.
If Device 1 Function 0 VGA enable bit is not set, then accesses to
I/O address range x3BCh–x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then
accesses to I/O address range x3BCh–x3BFh are forwarded to
PCI Express through Device 1 Function 0 if the address is within
the corresponding IOBASE and IOLIMIT, otherwise they remain
on the backbone.
MDA resources are defined as the following:
Memory:
I/O:
0B0000h–0B7FFFh
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not
used in decode)
0
RW
0b
Uncore
Any I/O reference that includes the I/O locations listed above, or
their aliases, will remain on the backbone even if the reference
also includes I/O locations not listed above.
The following table shows the behavior for all combinations of
MDA and VGA:
VGAEN MDAP Description
0
0
All References to MDA and VGA space are
not claimed by Device 1 Function 0.
0
1
1
0
Illegal combination
All VGA and MDA references are routed to
PCI Express Graphics Attach Device 1
Function 0.
1
1
All VGA references are routed to PCI Express
Graphics Attach Device 1 Function 0. MDA
references are not claimed by Device 1
Function 0.
VGA and MDA memory cycles can only be routed across PEG10
when MAE (PCICMD10[1]) is set. VGA and MDA I/O cycles can
only be routed across PEG10 if IOAE (PCICMD10[0]) is set.
Datasheet, Volume 2
75
INTEL [ INTEL ]
