Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
6–7h
0090h
RW1C, RO
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Signaled System Error (SSE)
This bit is set to 1 when Device 0 generates an SERR message
over DMI for any enabled Device 0 error condition. Device 0 error
conditions are enabled in the PCICMD, ERRCMD, and DMIUEMSK
registers. Device 0 error flags are read/reset from the PCISTS,
ERRSTS, or DMIUEST registers. Software clears this bit by writing
a 1 to it.
14
RW1C
0b
Uncore
Received Master Abort Status (RMAS)
This bit is set when the processor generates a DMI request that
receives an Unsupported Request completion packet. Software
clears this bit by writing a 1 to it.
13
12
11
RW1C
RW1C
RO
0b
0b
0b
Uncore
Uncore
Uncore
Received Target Abort Status (RTAS)
This bit is set when the processor generates a DMI request that
receives a Completer Abort completion packet. Software clears
this bit by writing a 1 to it.
Signaled Target Abort Status (STAS)
The processor will not generate a Target Abort DMI completion
packet or Special Cycle. This bit is not implemented and is
hardwired to a 0. Writes to this bit position have no effect.
DEVSEL Timing (DEVT)
These bits are hardwired to 00. Writes to these bit positions have
no effect. Device 0 does not physically connect to PCI_A. These
bits are set to 00 (fast decode) so that optimum DEVSEL timing
for PCI_A is not limited by the Host.
10:9
RO
RW1C
RO
00b
0b
Uncore
Uncore
Uncore
Master Data Parity Error Detected (DPD)
This bit is set when DMI received a Poisoned completion from PCH.
This bit can only be set when the Parity Error Enable bit in the PCI
Command register is set.
8
7
Fast Back-to-Back (FB2B)
This bit is hardwired to 1. Writes to these bit positions have no
effect. Device 0 does not physically connect to PCI_A. This bit is
set to 1 (indicating fast back-to-back capability) so that the
optimum setting for PCI_A is not limited by the Host.
1b
6
5
RO
RO
0h
0b
Reserved (RSVD)
66 MHz Capable (MC66)
Does not apply to PCI Express. Must be hardwired to 0.
Uncore
Uncore
Capability List (CLIST)
This bit is hardwired to 1 to indicate to the configuration software
that this device/function implements a list of new capabilities. A
list of new capabilities is accessed using register CAPPTR at
configuration address offset 34h. Register CAPPTR contains an
offset pointing to the start address within configuration space of
this device where the Capability Identification register resides.
4
RO
RO
1b
0h
3:0
Reserved (RSVD)
Datasheet, Volume 2
51
INTEL [ INTEL ]
