Processor Configuration Registers
Table 2-8.
PCI Device 0, Function 0 Configuration Space Register Address Map (Sheet 2
of 2)
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
89–8Fh
90–97h
RSVD
Reserved
0h
RO
Remap Base Address Register
Remap Limit Address Register
Top of Memory
0000000FFFF0
0000h
REMAPBASE
RW-L, RW-KL
00000000000
00000h
98–9Fh
A0–A7h
A8–AFh
REMAPLIMIT
TOM
RW-L, RW-KL
RW-L, RW-KL
RW-KL, RW-L
0000007FFFF0
0000h
Top of Upper Usable DRAM
00000000000
00000h
TOUUD
B0–B3h
B4–B7h
B8–BBh
BC–BFh
C0–DBh
DC–DFh
E0–E3h
E4–E7h
E8–EBh
BDSM
BGSM
Base Data of Stolen Memory
Base of GTT stolen Memory
TSEG Memory Base
Top of Low Usable DRAM
Reserved
00000000h
00100000h
00000000h
00100000h
0h
RW-KL, RW-L
RW-L, RW-KL
RW-L, RW-KL
RW-KL, RW-L
RO
TSEGMB
TOLUD
RSVD
SKPD
Scratchpad Data
Reserved
00000000h
0h
RW
RSVD
RO
CAPID0_A
CAPID0_B
Capabilities A
00000000h
00000000h
RO-FW, RO-KFW
RO-FW, RO-KFW
Capabilities B
2.5.1
VID—Vendor Identification Register
This register combined with the Device Identification register uniquely identifies any
PCI device.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
0–1h
8086h
RO
16 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Vendor Identification Number (VID)
PCI standard identification for Intel.
15:0
RO
8086h
Uncore
48
Datasheet, Volume 2
INTEL [ INTEL ]
