Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
4–5h
0006h
RO, RW
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Address/Data Stepping Enable (ADSTEP)
Address/data stepping is not implemented in the processor, and
this bit is hardwired to 0. Writes to this bit position have no
effect.
7
RO
0b
Uncore
Parity Error Enable (PERRE)
This bit controls whether or not the Master Data Parity Error bit in
the PCI Status register can bet set.
6
5
RW
RO
0b
0b
Uncore
0 = Master Data Parity Error bit in PCI Status register can NOT
be set.
1 = Master Data Parity Error bit in PCI Status register CAN be
set.
VGA Palette Snoop Enable (VGASNOOP)
The processor does not implement this bit and it is hardwired to a
0. Writes to this bit position have no effect.
Uncore
Uncore
Memory Write and Invalidate Enable (MWIE)
The processor will never issue memory write and invalidate
commands. This bit is therefore hardwired to 0. Writes to this bit
position will have no effect.
4
3
2
RO
RO
RO
0b
0h
1b
Reserved (RSVD)
Bus Master Enable (BME)
The processor is always enabled as a master on the backbone.
This bit is hardwired to a 1. Writes to this bit position have no
effect.
Uncore
Memory Access Enable (MAE)
The processor always allows access to main memory, except
when such access would violate security principles. Such
exceptions are outside the scope of PCI control. This bit is not
implemented and is hardwired to 1. Writes to this bit position
have no effect.
1
0
RO
RO
1b
0b
Uncore
Uncore
I/O Access Enable (IOAE)
This bit is not implemented in the processor and is hardwired to a
0. Writes to this bit position have no effect.
2.5.4
PCISTS—PCI Status Register
This status register reports the occurrence of error events on Device 0's PCI interface.
Since Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
6–7h
0090h
RW1C, RO
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
Detected Parity Error (DPE)
This bit is set when this Device receives a Poisoned TLP.
15
RW1C
0b
Uncore
50
Datasheet, Volume 2
INTEL [ INTEL ]
