Processor Configuration Registers
2.5.5
RID—Revision Identification Register
This register contains the revision number of Device 0. These bits are read only and
writes to this register have no effect.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
8h
00h
RO-FW
8 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Revision Identification Number (RID)
®
7:0
RO-FW
0h
Uncore
Refer to the Mobile 3rd Generation Intel Core™ Processor
Family Specification Update for the value of the RID register.
2.5.6
CC—Class Code Register
This register identifies the basic function of the device, a more specific sub-class, and a
register-specific programming interface.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
9–Bh
060000h
RO
24 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Base Class Code (BCC)
This is an 8-bit value that indicates the base class code for the
Host Bridge device. This code has the value 06h, indicating a
Bridge device.
23:16
RO
06h
00h
00h
Uncore
Uncore
Uncore
Sub-Class Code (SUBCC)
This is an 8-bit value that indicates the category of Bridge into
which the Host Bridge device falls. The code is 00h indicating a
Host Bridge.
15:8
7:0
RO
RO
Programming Interface (PI)
This is an 8-bit value that indicates the programming interface of
this device. This value does not specify a particular register set
layout and provides no practical use for this device.
52
Datasheet, Volume 2
INTEL [ INTEL ]
