Processor Configuration Registers
2.5
PCI Device 0 Function 0 Configuration Space
Registers
Table 2-8.
PCI Device 0, Function 0 Configuration Space Register Address Map (Sheet 1
of 2)
Address
Offset
Register
Symbol
Register Name
Reset Value
Access
0–1h
2–3h
VID
DID
Vendor Identification
8086h
0150h
0006h
0090h
00h
RO
RO-FW, RO-V
RO, RW
RW1C, RO
RO-FW
RO
Device Identification
PCI Command
4–5h
PCICMD
PCISTS
RID
6–7h
PCI Status
8h
Revision Identification
Class Code
9–Bh
C–Dh
Eh
CC
060000h
0h
RSVD
HDR
Reserved
RO
Header Type
00h
RO
F–2Bh
2C–2Dh
2E–2Fh
30–33h
34h
RSVD
SVID
SID
Reserved
0h
RO
Subsystem Vendor Identification
Subsystem Identification
Reserved
0000h
0000h
0h
RW-O
RW-O
RO
RSVD
CAPPTR
RSVD
Capabilities Pointer
Reserved
E0h
RO
35–3Fh
0h
RO
PCI Express Egress Port Base Address
00000000000
00000h
40–47h
48–4Fh
PXPEPBAR
MCHBAR
RW
RW
Host Memory Mapped Register Range Base
00000000000
00000h
50–51h
52–53h
54–57h
58–5Bh
GGC
RSVD
DEVEN
PAVPC
GMCH Graphics Control Register
Reserved
0028h
0h
RW-L, RW-KL
RO
Device Enable
0000209Fh
00000000h
RW-L, RO, RW
RW-L, RW-KL
Protected Audio Video Path Control
DMA Protected Range
RW-L, RO-V,
RW-KL
5C–5Fh
60–67h
68–6Fh
70–77h
78–7Fh
DPR
00000000h
PCI Express Register Range Base Address
00000000000
00000h
PCIEXBAR
DMIBAR
RW, RW-V
RW
Root Complex Register Range Base Address 00000000000
00000h
Intel Management Engine Base Address
Register
0000007FFFF0
0000h
MESEG_BASE
MESEG_MASK
RW-L
Intel Management Engine Limit Address
Register
00000000000
00000h
RW-L, RW-KL
80h
81h
82h
83h
84h
85h
86h
87h
PAM0
PAM1
PAM2
PAM3
PAM4
PAM5
PAM6
LAC
Programmable Attribute Map 0
Programmable Attribute Map 1
Programmable Attribute Map 2
Programmable Attribute Map 3
Programmable Attribute Map 4
Programmable Attribute Map 5
Programmable Attribute Map 6
Legacy Access Control
00h
00h
00h
00h
00h
00h
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
Reserved
RW-LV, RW-L,
RW-KL, RO
88h
RSVD
02h
Datasheet, Volume 2
47
INTEL [ INTEL ]
