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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.5.12  
MCHBAR—Host Memory Mapped Register Range Base  
Register  
This is the base address for the Host Memory Mapped Configuration space. There is no  
physical memory within this 32 KB window that can be addressed. The 32 KB reserved  
by this register does not alias to any PCI 2.3 compliant memory mapped space. On  
reset, the Host MMIO Memory Mapped Configuration space is disabled and must be  
enabled by writing a 1 to MCHBAREN [Device 0, offset 48h, bit 0].  
All the bits in this register are locked in Intel TXT mode.  
The register space contains memory control, initialization, timing, and buffer strength  
registers; clocking registers; and power and thermal management registers.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
48–4Fh  
0000000000000000h  
RW  
64 bits  
Size:  
BIOS Optimal Default  
0000000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
63:39  
RO  
0h  
Reserved (RSVD)  
Host Memory Mapped Base Address (MCHBAR)  
This field corresponds to bits 38:15 of the base address Host  
Memory Mapped configuration space. BIOS will program this  
register resulting in a base address for a 32 KB block of  
contiguous memory address space. This register ensures that a  
naturally aligned 32 KB space is allocated within the first 512 GB  
of addressable memory space. System software uses this base  
address to program the Host Memory Mapped register set. All the  
bits in this register are locked in Intel TXT mode.  
38:15  
RW  
000000h  
Uncore  
14:1  
0
RO  
0h  
0b  
Reserved (RSVD)  
MCHBAR Enable (MCHBAREN)  
0 = Disable. MCHBAR is disabled and does not claim any  
memory  
1 = Enable. MCHBAR memory mapped accesses are claimed and  
decoded appropriately  
RW  
Uncore  
This register is locked by Intel TXT.  
2.5.13  
GGC—GMCH Graphics Control Register  
All the bits in this register are Intel TXT lockable.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
50–51h  
0028h  
RW-L, RW-KL  
16 bits  
00h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
15  
14  
RO  
RW-L  
RO  
0h  
0b  
0h  
Reserved (RSVD)  
Reserved (RSVD)  
Reserved (RSVD)  
Uncore  
13:10  
Datasheet, Volume 2  
55