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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
2.5.10  
CAPPTR—Capabilities Pointer Register  
The CAPPTR provides the offset that is the pointer to the location of the first device  
capability in the capability list.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
34h  
E0h  
RO  
8 bits  
Size:  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Capabilities Pointer (CAPPTR)  
Pointer to the offset of the first capability ID register block. In  
this case the first capability is the product-specific Capability  
Identifier (CAPID0).  
7:0  
RO  
E0h  
Uncore  
2.5.11  
PXPEPBAR—PCI Express* Egress Port Base Address  
Register  
This is the base address for the PCI Express Egress Port MMIO Configuration space.  
There is no physical memory within this 4 KB window that can be addressed. The 4 KB  
reserved by this register does not alias to any PCI 2.3 compliant memory mapped  
space. On reset, the EGRESS port MMIO configuration space is disabled and must be  
enabled by writing a 1 to PXPEPBAREN [Device 0, offset 40h, bit 0].  
All the bits in this register are locked in Intel TXT mode.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/0/0/PCI  
40–47h  
0000000000000000h  
RW  
64 bits  
Size:  
BIOS Optimal Default  
000000000h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
63:39  
RO  
0h  
Reserved (RSVD)  
PCI Express Egress Port MMIO Base Address (PXPEPBAR)  
This field corresponds to bits 38:12 of the base address PCI  
Express Egress Port MMIO configuration space. BIOS will  
program this register resulting in a base address for a 4 KB block  
of contiguous memory address space. This register ensures that  
a naturally aligned 4 KB space is allocated within the first 512 GB  
of addressable memory space. System software uses this base  
address to program the PCI Express Egress Port MMIO register  
set. All the bits in this register are locked in Intel TXT mode.  
38:12  
RW  
0000000h  
Uncore  
11:1  
0
RO  
0h  
0b  
Reserved (RSVD)  
PXPEPBAR Enable (PXPEPBAREN):  
0 = Disable. PXPEPBAR is disabled and does not claim any  
memory  
1 = Enable. PXPEPBAR memory mapped accesses are claimed  
and decoded appropriately  
RW  
Uncore  
This register is locked by Intel TXT.  
54  
Datasheet, Volume 2