Processor Configuration Registers
2.5.2
DID—Device Identification Register
This register combined with the Vendor Identification register uniquely identifies any
PCI device.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
2–3h
0150h
RO-FW, RO-V
16 bits
Size:
Reset
Value
RST/
PWR
Bit
Access
Description
Device Identification Number MSB (DID_MSB)
15:4
RO-FW
015h
00b
Uncore
Uncore
Uncore
This is the upper part of device identification assigned to the
processor.
Device Identification Number SKU (DID_SKU)
This is the middle part of device identification assigned to the
processor.
3:2
1:0
RO-V
Device Identification Number LSB (DID_LSB)
This is the lower part of device identification assigned to the
processor.
RO-FW
00b
2.5.3
PCICMD—PCI Command Register
Since Device 0 does not physically reside on PCI_A many of the bits are not
implemented.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
0/0/0/PCI
4–5h
0006h
RO, RW
16 bits
00h
Size:
BIOS Optimal Default
Reset
Value
RST/
PWR
Bit
Access
Description
15:10
RO
0h
Reserved (RSVD)
Fast Back-to-Back Enable (FB2B)
This bit controls whether or not the master can do fast back-to-
back write. Since Device 0 is strictly a target this bit is not
implemented and is hardwired to 0. Writes to this bit position
have no effect.
9
RO
0b
Uncore
SERR Enable (SERRE)
This bit is a global enable bit for Device 0 SERR messaging. The
processor communicates the SERR condition by sending an SERR
message over DMI to the PCH.
1 = The processor is enabled to generate SERR messages over
DMI for specific Device 0 error conditions that are
individually enabled in the ERRCMD and DMIUEMSK
registers. The error status is reported in the ERRSTS,
PCISTS, and DMIUEST registers.
0 = The SERR message is not generated by the Host for Device
0.
8
RW
0b
Uncore
This bit only controls SERR messaging for Device 0. Other
integrated devices have their own SERRE bits to control error
reporting for error conditions occurring in each device. The
control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
0 = Device 0 SERR disabled
1 = Device 0 SERR enabled
Datasheet, Volume 2
49
INTEL [ INTEL ]
